The invention relates to a method and arrangement for forming reception pulses in a receiver operating according to the IrDA standard, wherein the output signals of an upstream comparator that recognizes light pulses are used for evaluation by a downstream arrangement, and re-formed and emitted as pulses.
In data transfer by means of infrared light according to the IrDA standard (Infrared Data Association) in the specification of FIR (Fast Infrared), for example, wherein the 4 PPM (four pulse position modulation) modulation type is used, post-processing steps must be done for the output pulses produced by a comparator. In this modulation type two data bits are consolidated to one data bit pair (DBP). A period of 500 ns, divided into four 125 ns time slices, is available for transferring a DBP. One position or one chip, which is represented by an optical pulse, is discretely allocated to each of the four possible 2-bit words. Thus the coding depends on the position of the single pulse within the 500 ns time period. Consequently it may happen that the fourth position of the code “n” is occupied and immediately following the first position of the code “n+1”. In this case both single pulses merge into a double-wide [viz. double-duration] so-called double pulse. Due to the properties of this 4 PPM modulation type both single pulses with a 125 ns pulse duration and double-pulses with 250 ns pulse duration are transferred and made recognizable as such at the output of a circuit for post-processing of the pulses produced by the comparator at the digital output RxD of a receiver.
An amplifier built into the infrared receiver must have an appropriately large bandwidth in order satisfy these transfer requirements. In practice, due to the high power consumption in a correspondingly large bandwidth, a limited bandwidth is available whose value is defined by the requirements for transferring the single and the double pulses. Thus in the critical case, depending on the input current amplitude, there is an lengthening of the single pulses and a shortening of the double impulses within the transfer range.
A circuit for post-processing of the output signals of a comparator consists in the simplest case of a monoflop for forming the single pulse. In the case of transferring a double pulse a combinatorial lengthening of the single pulse supplied by the monoflop corresponding to the amplifier dynamics of said pulse. Thus, although the single pulse is newly produced, the double pulse is composed only from a produced single pulse and the pulse remnant dependent on and distorted by the amplifier dynamics.
Furthermore, for example as taught by U.S. Pat. No. 6,198,766 B1, more complex circuits for subsequent processing are known which define an ideal time pattern using an external time basis and synchronize the comparator pulses either in this pattern or even modify them adaptively.
The very simple and space-optimum solution of a single monoflop for forming the single pulses has the significant drawbacks that on the one hand excessively long single pulses with strongly varying pulse duration at the comparator output are stretched beyond the monoflop time by the logic required for the transfer of the double pulses at the output RxD of the subsequent processing circuit. On the other hand the double pulse itself is transferred only combinatorily and is not processed at all. Accordingly, at the RxD output only the direct and unstable pulse duration of the comparator appears at all times. Both effects can result, independently of each other, in a stalling of the data transfer according to the IrDA standard, if in certain dynamic areas the pulse durations no longer conform with the requirements imposed on minimum and/or maximum pulse duration requirement. On the other hand, the demand of transfer of the light pulses as faithfully as possible to the pulse via the amplifier compels greater amplifier bandwidth. This results on the one hand in high operating power and on the other hand, because of the low lower cut-off frequency, for example, large, area intensive coupling capacities.
Systems approaches with external synchronization require either an additional clock input or an integrated quartz oscillator that generates an adequate time base. For the jitter requirements of 20 ns given in the FIR specification to be maintained this solution requires sampling rates of at least 40 MHz which is equivalent also to the clock rate of the I/O circuit. Along with a circuit that is more complex and requires more space with this timing and its utilization there is also an interference source on the chip which is isolated from the sensitive amplifier complex by means of additional shielding schemes that also occupy considerable space.